The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
Apr. 22, 1998
William R. Crumly, Anaheim, CA (US);
Packard Hughes Interconnect Company, Irvine, CA (US);
Abstract
Generally, the invention includes a product for and a method of wafer scale burn-in testing. The product may include a substrate or semiconductor device having a nonplanar surface (multi-layer substrate), an interposer layer over the nonplanar surface and electrical traces on the interposer having raised electrical features for connecting to contact pads on a semiconductor wafer. The interposer layer may take on a variety of configurations and compositions. The interposer layer may be an adhesive layer, or a combination of a flexible layer for supporting the electrical traces and raised features, and a compressible layer. Vias may be provided from the electrical traces down to contact pads on the substrate or device having a nonplanar surface. Alternatively, electrical traces having a first and second raised features extending in opposite directions may be utilized to make a connection between the wafer and the multi-layer substrate.