Method of esd protection scheme

Abstract

An integrated circuit device is provided comprising an integrated circuit pad, an internal integrated circuit, and an ESD protection circuit. The internal integrated circuit is conductively coupled to the integrated circuit pad so as to define a primary electrical path from the integrated circuit pad to the internal integrated circuit. The ESD protection circuit is conductively coupled to the integrated circuit pad so as to define a secondary electrical path from the integrated circuit pad to the ESD protection circuit. The ESD protection circuit comprises a semiconductor structure arranged to define a doped silicon substrate, a drain region, a source region, an electrically insulating region, and a gate structure. The drain region is formed in the silicon substrate and is conductively coupled to the integrated circuit pad via the secondary electrical path. The source region is formed in the silicon substrate and is conductively coupled to a relatively low electrical potential. The electrically insulating region is formed in the silicon substrate between the drain region and the source region. The gate structure is conductively coupled to a relatively low electrical potential and is arranged to define an incipient inversion layer in the drain region upon application of a relatively high electrical potential to the integrated circuit pad. The gate structure and the electrically insulating region are arranged to define an active gate region limited to extend from the drain region to the electrically insulating region.