The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2001

Filed:

Mar. 24, 2000
Applicant:
Inventors:

Kuan-Lun Chang, Chutung Hsinch, TW;

Bing-Yue Tsui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the CMOS and bipolar devices, such as the creation of an N type buried layer, used in one region for isolation of PFET devices, and used in a second region, of the semiconductor substrate, as a subcollector region, for the bipolar device. Features of the BiCMOS process include the formation of N well, and P well regions, for CMOS device, as well as the use of an epitaxial silicon layer, to allow optimum bipolar characteristics to be achieved.


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