The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2001
Filed:
Mar. 03, 1998
Bharat Sastri, Pleasanton, CA (US);
Thomas Alexander, San Jose, CA (US);
Chitranjan N. Reddy, Los Altos Hills, CA (US);
Alliance Semiconductor Corporation, Santa Clara, CA (US);
Abstract
The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit. In a third embodiment of the present invention, the high speed/low speed interface subsystem comprises all the elements of the second embodiment and a memory controller. The embodiments of the present invention could be implemented with discrete components or could be implemented on a single semiconductor substrate.