Fast comparator suitable for bist and bisr applications

Abstract

Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted. A first clock transistor may be coupled between the first node and a second node and configured to conduct when a clock signal is asserted, and a second clock transistor may be coupled between a positive source voltage and the second node and configured to conduct when the clock signal is de-asserted. If a pull-up resistance is provided, this allows the first or second node to indicate the match or mismatch of the input words. Further robustness may be provided by a Schmitt-trigger configuration coupled to the second node.