The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2001

Filed:

Feb. 17, 2000
Applicant:
Inventor:

Hsu Kai Yang, Pleasanton, CA (US);

Assignee:

Kaitech Engineering, Inc., Pleasonton, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/604 ;
U.S. Cl.
CPC ...
G11C 1/604 ;
Abstract

A semiconductor memory device includes an erase line, a common line, and a first transistor coupled between the conductive line and the common line. The memory device includes a plurality of memory cells and bit lines, each memory cell including a program line, a memory transistor, and a tunneling capacitor having a first node coupled to the floating gate. A second transistor is coupled between the program line and another node of the tunneling capacitor. An access transistor is coupled to the memory transistor and the bit line. The second transistor may be a depletion-type transistor, as may be the first transistor that is coupled to the erase line. The memory cell may also be implemented as a single-polysilicon memory structure.


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