The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2001
Filed:
Dec. 15, 1999
Frederick G. Wall, Garland, TX (US);
Bernhard H. Andresen, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A fail-safe Input/Output buffer bias circuit for digital CMOS chips provides protection for Input/Output buffers which have high voltages applied to the Input/output node and are subjected to power supply failure resulting in a collapsing supply voltage decaying to zero volts while said Input/output circuit has a high voltage remaining applied to its Input/output node. The Input/output buffer bias circuit is comprised of a sensing circuit and a bias generator circuit which acts to drive protection transistors in a manner which optimally minimizes the voltage impressed on input or output devices under all conditions which could persist in the event of V,supply voltage failure. Protection circuitry holds all three combinations of voltage stress, gate-to-source, gate-to-drain, and drain-to-source voltages, to acceptable levels.