The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2001
Filed:
Apr. 20, 2000
John Deane Coddington, Cedar Park, TX (US);
Chau-Shing Hui, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A system (,) has a shifting delay circuit (,) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (,) which includes a delay line (,) which provides a variable delay for delaying the source clock. The delay line (,) has its delay varied by a counter (,). The counter (,) is incremented in order to change the delay. The shifting delay circuit (,) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (,) and delay line (,). The delay line (,), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (,).