The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2001
Filed:
Jan. 31, 2000
Jiming Zhang, Austin, TX (US);
Dean J. Denning, Del Valle, TX (US);
Sam S. Garcia, Austin, TX (US);
Scott K. Pozder, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
The formation of an adhesion/interlayer region (,) of a semiconductor substrate device (,) before barrier layer (,) deposition provides improved adhesion of the barrier layer (,) to the underlying dielectric (,) and increases strength to the next interconnect layer without altering the function of the barrier layer (,) to limit Cu diffusion into the dielectric substrate (,). The adhesion/interlayer region (,) is formed in an inlaid structure (,) of a semiconductor wafer. The inlaid structure (,) is connected to upper or lower metal layers through vias in the dielectric layer (,) to a copper layer. The adhesion/interlayer region is formed by flowing a treating gas in a glow discharge process of the dielectric substrate in a chamber either attached or separated from the barrier deposition chamber (,). The barrier layer (,) and the adhesion/interlayer region (,) can be formed in this inlaid structure (,) of a semiconductor wafer. The treating gas (,) can be nitrogen, hydrogen, gases containing carbon atoms, or some other suitable gas.