Method and structure to make planar analog capacitor on the top of a sti structure

Abstract

A new method is provided to create a capacitor over the surface of STI regions. The STI regions are first created in the surface of the substrate, a layer of sacrificial oxide is next blanket deposited over the substrate (thereby including the surface of the created STI regions). A depletion stop region overlying densely spaced STI regions is formed in the surface of the substrate by N+ ion implantation, N-well and P-well regions are formed surrounding the depletion stop region. An insulation layer is deposited. The sacrificial oxide and insulation layers are patterned and etched leaving the sacrificial oxide and the insulation layer in place where the capacitor is to be created. A layer of gate oxide is formed over the surface of the substrate, a layer of poly 2 is deposited for the bottom plate and the gate electrode. The conductivity of the gate electrode and the bottom plate of the capacitor is established by performing a selective N+ implant into the layer of poly 2 where the gate electrode and the bottom plate of the capacitor are to be formed. A layer of dielectric is deposited for the capacitor dielectric, a layer of in-situ doped poly 3 is deposited for the top plate of the capacitor. The layers of poly 3, dielectric and poly 2 are etched forming the capacitor structure and the gate electrode structure.