The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2001

Filed:

Dec. 23, 1999
Applicant:
Inventors:

Ajay P. Giri, Poughkeepsie, NY (US);

John U. Knickerbocker, Hopewell Junction, NY (US);

David C. Long, Wappingers Falls, NY (US);

Subhash L. Shinde, Cortlandt Manor, NY (US);

Lisa M. Studzinski, Collierville, TN (US);

Rao V. Vallabhaneni, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/148 ; H01L 2/150 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/148 ; H01L 2/150 ;
Abstract

A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.


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