The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Dec. 11, 1998
Timothy S. Leight, Austin, TX (US);
Terence M. Potter, Austin, TX (US);
James S. Blomgren, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
A syntax statement describing an N-NARY or a CMOS logic circuit having one, and only one, possible configuration of transistors is disclosed. The syntax statement comprises a signal naming convention and one or more gate instantiations using a gate instantiation syntax that includes one or more gate output signal variables described using the signal naming convention, one or more gate operators, and one or more gate expressions using a gate expression syntax that is interpreted to describe the specific transistor configuration of the logic circuit. The signal naming convention includes one or more of the following fields: optional bit and descriptor, signal degree, evaluation, and clock phase. The gate expression syntax further comprises one or more of the following syntaxes: mux select, arithmetic, logical, multiple output, capacitance isolation, or shared node.