The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2001

Filed:

Jul. 20, 2000
Applicant:
Inventors:

Ju-seok Maeng, Suwon, KR;

In-ho Hyun, Kyungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/166 ;
U.S. Cl.
CPC ...
H01L 2/166 ;
Abstract

A chip scale package (CSP) fabricating method is provided. In this method, CSP chips are fabricated on a wafer and subjected to an electric die sorting (EDS) process. Then, CSP chips determined to be non-defective through the FDS process are packaged into a CSP strip. and the CSP strip is subjected to a final test. Then, the CSP strip subjected to the final test is singulated into individual CSPs. Following this, the CSPs are surface-mounted on a module board. Substantially all of the CSPs on the CSP module board are subsequently burn-in tested. As a result, productivity is improved, and manufacturing costs are reduced.


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Maeng, Ju-seok. (2001). Method of fabricating chip scale package (U.S. Patent No. 6287878). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6287878

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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