The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2001
Filed:
Dec. 22, 1998
Yuejian Wu, Kanata, CA;
Paul P. Soong, Nepean, CA;
Nortel Networks Limited, Montreal, CA;
Abstract
An interconnect delay test uses the IEEE 1149.1 standard test access port (TAP) controller. No modification of standard boundary cells is required. Since the standard boundary scan cells are used, circuit board and/or backplane interconnect delay tests do not affect ASIC (application specific integrated circuit) designs. It allows board and system designers to add new interconnect AC tests for any signals at any time without modification of ASICs. Since the method has no impact on the operations of the standard TAP controller, it is possible to use available test softwares for interconnect DC tests to perform the proposed delay test. The method can also be integrated as part of in-system interconnect tests.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile