The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2001
Filed:
Mar. 29, 1999
Vijai Komar N. Chhagan, Belgrave, GB;
Yelehanka Machandramurthy Pradee, Singapore, SG;
Mei Sheng Zhou, Singapore, SG;
Henry Gerung, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A method to fabricate a floating gate with a sloping sidewall for a Flash Memory is described. Field oxide isolation regions are provided in the substrate. A silicon oxide layer is provided overlying the isolation regions and the substrate. A first polysilicon layer is deposited overlying the silicon oxide layer. A photoresist layer is deposited overlying the first polysilicon layer. The photoresist layer is etched to remove sections of the photoresist as defined by photolithographic process. The photoresist layer, the first polysilicon layer, and the silicon oxide layer are etched in areas uncovered by the photoresist layer to create structures with sloping sidewall edges. The photoresist layer is etched away. An interpoly dielectric layer is deposited overlying the structures, the sloping sidewall edges, and the isolation regions. A second polysilicon layer is deposited overlying the interpoly dielectric and the fabrication of the integrated circuit device is completed.