Clock driver with instantaneously selectable phase and method for use in data communication systems

Abstract

A clock driver providing a clock signal, from an input clock signal, that has instantaneously selectable phase and methods for synchronizing data transfers in a multi-signal bus communication system. A clock driver of the present invention generates an output clock signal from an input clock signal having a periodic wave form and provides the flexibility for selecting or changing the magnitude of the phase-offset of the output clock signal, in relationship to the input clock signal, for desired clock periods and optionally desired half-clock periods. A method is provided for the self-calibration of critical delay elements. The present invention also includes a method for synchronizing data transfers between a bus master device that is clocked by a system clock and a plurality of synchronous DRAM devices (SDRAM) that are clocked by a local clock; the local clock has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. A Dual In Line Module (DIMM) of the present invention receives a system clock signal and provides a local clock signal to an array of SDRAM devices, wherein the local clock signal has, in relationship to the system clock signal, a first phase-offset for read cycles and a second phase-offset for write cycles. Optionally the magnitude of the phase-offset of the local clock signal is selectable through software providing the flexibility to support a method for determining the optional phase-offsets by software using an iterative process involving trial and error.