Three-dimensional ferroelectric capacitor structure for nonvolatile random access memory cell

Abstract

A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduce the lateral size of the capacitor structure. The fabrication of the capacitor structure is compatible to conventional CMOS processing technology, in which the resulting capacitor structure may become embedded in a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS transistor to produce a one-transistor-one-capacitor nonvolatile memory cell. Preferably, the three-dimensional electrode plates are made of platinum (Pt) or iridium (Ir) and the capacitor dielectric is a ferrous-electric material, such as lead-zirconate-titanate (PZT) or barium-strontium-titanate (BST). The electrode plates and the capacitor dielectric are formed by depositing layers of appropriate materials within the cavity, which has been formed to include tapering walls in a dielectric layer of the layer stack. Next, portions of the deposited layers, or a “capacitor stack,” are removed down to the surface of the dielectric layer such that only the materials that were deposited within the cavity of the dielectric layer are left. The remaining materials form the electrode plates, as well as the capacitor dielectric. In the preferred embodiment, the selective removal of the capacitor stack portions is accomplished by planarizing the capacitor stack using a Chemical Mechanical Planarization (CMP) process. Alternatively, a sputter etch-back process may be utilized to remove the capacitor stack portions.