The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2001

Filed:

Mar. 18, 1998
Applicant:
Inventors:

Takao Watanabe, Fuchu, JP;

Takuya Fukuda, Kodaira, JP;

Norio Hasegawa, Hinode-machi, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 2/994 ; H01L 3/1119 ;
Abstract

The present invention relates to a semiconductor device that includes a dynamic memory and logic circuits that are integrated on a single chip and that can avoid noise problems and signal delay. The portion above the memory is shielded with a shielding conductor that is biased to an equipotential. Wirings between logical blocks and bonding pads or between logical blocks are passed over the conductive layer. Wiring for logic circuits can be done in the same metal wiring layer in which the shielding conductor is provided. The shielding conductor can have a mesh-like structure to improve its integrity and wirings can be passed over conductive portions of the shielding layer to be protected from noise. In addition to the dynamic memory, other memories and analog circuits can be used instead of or in combination with the dynamic memory.


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