The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2001
Filed:
Nov. 13, 1998
Kenneth D. Amstutz, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
The present invention comprises a method and apparatus for built-in self-test of logic circuitry for logic under test. The logic under test comprises a plurality of test points, each test point having a plurality of nodes. The test circuitry comprises a linear finite state machine. The linear finite state machine generates subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine. Moreover, the contents of the linear finite state machine are readable or writable via scan. The preferred implementation also comprises a test data bus coupled between the logic under test and the linear finite state machine. The test data bus is configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.