The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2001
Filed:
Aug. 05, 1994
Applicant:
Inventors:
Eitan Rosen, Haifa, IL;
Jack Doweck, Haifa, IL;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/208 ; G06F 1/314 ;
U.S. Cl.
CPC ...
G06F 1/208 ; G06F 1/314 ;
Abstract
A cache memory circuit is disclosed that includes a store hit buffer that buffers write operations to the cache memory circuit and that removes write operations from the critical speed path for the cache memory array. The store hit buffer includes circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer and circuitry for merging the write operation from the store hit buffer with the read operation.
Rosen, Eitan. (2001). N-way set-associative cache memory which includes a store hit buffer for improved data access (U.S. Patent No. 6272595). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6272595
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile