The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2001

Filed:

Jan. 14, 1998
Applicant:
Inventors:

Min-Liang Chen, Hsinchu, TW;

Nan-Hsiung Tsai, Hsinchu, TW;

Assignee:

Mosel Vitelic, Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ;
Abstract

A dynamic random access memory (DRAM) integrated circuit (,). The DRAM (,) includes a recessed region (,) defined in a semiconductor substrate (,). This recessed region has substantially vertical sides (,) extending from a bottom surface (,). A field effect transistor (,) is defined adjacent to the recessed region (,). A capacitor structure, including a lower capacitor plate (,), a capacitor dielectric (,), and an upper capacitor plate (,), is defined in the recessed region (,) and over the field effect transistor (,), thereby providing a greater capacitor surface.


Find Patent Forward Citations

Chen, Min-Liang. (2001). High density memory structure (U.S. Patent No. 6271556). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6271556

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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