Method for making improved polysilicon emitters for bipolar transistors on bicmos integrated circuits

Abstract

A method for making an improved polysilicon emitter for a bipolar transistor in a BiCMOS integrated circuit is achieved. The method uses a novel stacked undoped amorphous silicon layer and a doped polysilicon layer. The polysilicon layer is doped by ion implantation while the amorphous silicon layer remains undoped. The stacked layer is patterned to form a polysilicon emitter source over the bipolar transistor, while concurrently forming gate electrodes for the FETs. The undoped amorphous silicon layer retards the diffusion from the doped polysilicon to provide a shallower emitter junction during subsequent thermal processing. At a later step a rapid thermal anneal (RTA) is carried out in which the amorphous silicon layer provides better control of the diffused emitter depth (junction) while concurrently activating the implant dopant in the FET source/drain areas. The better control of the shallow emitter depth over the conventional doped polysilicon emitter results in a smaller standard deviation of the current gain. Also the collector-to-emitter breakdown voltage is increased, and the reduced junction capacitance increases the cutoff frequency.