The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2001
Filed:
Mar. 11, 1999
Michael K. Templeton, Atherton, CA (US);
Bharath Rangarajan, Santa Clara, CA (US);
Kathleen R. Early, Santa Clara, CA (US);
Terry Manchester, Los Gatos, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
The present invention relates to wafer alignment. A reticle is employed which includes, a design and first and second alignment marks. The second alignment mark is symmetric to the first alignment mark such that a reticle center point is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark in wafer alignment substantially facilitates mitigation of overlay error.