Method and apparatus for logic synchronization

Abstract

The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate. The phase of an individual local clock signal overlaps an earlier phase local clock signal by an amount approximately equal to the overlap of the phase of the next individual local clock signal. The first dynamic logic gate, the intermediate dynamic logic gate(s), and the last dynamic logic gates couple such that an individual dynamic logic gate with an individual local clock signal and phase may only provide a signal to the next individual dynamic logic gate that uses a next phase local clock signal where the gates may couple together in series, in a feed back loop, or a feed forward loop.