The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2001

Filed:

Feb. 26, 1999
Applicant:
Inventors:

Thomas J. Mozdzen, Gilbert, AZ (US);

Orlando Davila, Queen Creek, AZ (US);

Christopher P. McAllister, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

A boundary scan cell for testing an integrated circuit comprises an output buffer for driving a pad of the integrated circuit, a capture register coupled to the pad through the output buffer, and an input buffer drives a signal present at the pad to a node coupled to core logic of the IC. A first multiplexer is included to have a first input coupled to the node, a second input coupled to data of a previous scan stage, and an output coupled to the capture register. Logic circuitry selectively enables/disables the input and output buffers responsive to first and second control signals such that the I/O buffers can drive the pad and, at the same time, drive the input buffer, the output of which is coupled to the input of the capture register.


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