Synchronous dram having posted cas latency and method for controlling cas latency

Abstract

A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, reading or writing operations in units of clock cycles, a first method of programing the delay time as a mode register set (MRS) and a second method of detecting the delay time using an internal signal and an external signal, are provided. In the second method, the SDRAM can include a counter for controlling the CAS latency. This counter controls the CAS latency of the SDRAM by generating a signal for controlling the CAS latency according to the number of clock cycles of a clock signal from the generation of a row access command to a column access command in the same memory bank and reading the signal. It is therefore possible to appropriately perform a posted CAS latency operation and a general CAS latency operation by the SDRAM without an additional MRS command according to this SDRAM and the method of controlling the CAS latency.