The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2001

Filed:

Apr. 19, 2000
Applicant:
Inventor:

Hidenori Uehara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

A memory circuit includes a memory cell array having word lines, bit lines and memory cells, and a word line reset circuit for applying an activation level to a word line that is selected, and for applying a lower level which is lower than a deactivation level to the word line when it is non-selected. The word line reset circuit includes a first driver for applying the activation level to the selected word line during a first selected period, a second driver for applying the deactivation level to the word line during a second select period after the first select period, and a third driver for applying the lower level to the word line during a period other than the first and second select periods.


Find Patent Forward Citations

Uehara, Hidenori. (2001). Memory circuit including word line reset circuit and method of resetting word line (U.S. Patent No. 6262934). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6262934

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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