The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2001
Filed:
Jun. 22, 2000
Geordie Braceras, Essex Junction, VT (US);
William F. Pokorny, Jericho, VT (US);
Alan L. Roberts, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method to statically balance Silicon-On-Insulator (SOI) parasitic effects is disclosed. Additionally, eight device Static Random Access Memory (SRAM) cells using the method are provided. A balanced output stage that creates a particular set of parasitic effects, as seen by a node connected to the output of the balanced output stage, is provided. If the balanced output stages are used at both outputs of a SRAM cell, the nodes to which the outputs of the balanced output stages are connected will see the same parasitic effects when the transistors in the balanced output stages are off. Thus, the balanced output stages can create the same effect on both the true and complement bitlines of an SOI SRAM, thereby balancing both of these lines and improving access times.