The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2001

Filed:

Dec. 18, 1998
Applicant:
Inventor:

Jong-Min Park, Kyunggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/606 ;
U.S. Cl.
CPC ...
G11C 1/606 ;
Abstract

The disclosure is a nonvolatile semiconductor memory having a plurality of memory cells, the memory cells being programmed and erased. The memory comprises a memory cell array having the memory cells arranged in a matrix, a sense amplifier for detecting a state of the memory cell, an input/output buffer for receiving an output of the sense amplifier and for generating an output responding to the output of the sense amplifier, a verifying circuit for generating an output responding to the output of the input/output buffer, and a control logic block for receiving signals relevant to verifying operations after programming and erasing and for generating signals controlling the input/output buffer and verifying circuit. The verifying operations for programmed and erased cells are conductive through the sense amplifier, the input/output buffer and verifying circuit, in common.


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