The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Apr. 19, 1999
Thomas Laursen, Tempe, AZ (US);
SpeedFam-IPEC Corporation, Chandler, AZ (US);
Abstract
A method of reducing dishing and erosion of surfaces of inlaid material on semiconductor wafers. The method includes forming a sacrificial deposit or layer over at least down features of the patterned surface of the fill layer, that has a lower rate of removal during chemical-mechanical polishing than the fill layer. Elevated caps of sacrificial deposit are formed over inlaid fill material prior to pattern clearing. In CMP pattern clearing, the caps are removed and polishing proceeds at a faster rate on the slightly elevated inlaid fill upper surfaces until they are coplanar with surrounding patterned substrate. Chemical-mechanical polishing can be carried out in a single step, or in multiple steps, to produce the desired result.