Method for forming an embedded memory and a logic circuit on a single substrate

Abstract

A method for forming an integrated circuit device that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate is disclosed. The substrate has a transfer field effect transistor (FET) with a first gate electrode and a first source/drain region formed in and on a embedded DRAM region of the substrate and has a logic FET with a second gate electrode and a second source/drain region formed in and on a logic circuit region of the substrate. Next, a dielectric layer was deposited over the exposing surface of said transfer FET and above of the logic FET. Moreover, the dielectric layer was polished until upper surface of the first gate electrode and the second gate electrode is exposed. Subsequently, a photoresist layer is formed over the dielectric layer and the first gate electrode. And then the dielectric layer was etched until upper surface of the logic FET is exposed. Next, the photoresist layer was removed. Finally, a self-aligned silicide layer was deposited simultaneously over the exposed second gate electrode, over the second source/drain region and over the exposed first gate electrode.