Method for forming twin gate cmos

Abstract

A method for forming an adapted small dimension and more quality fabrication is disclosed. In one embodiment, the present invention provides a twin gate CMOS, which includes isolations formed in a semiconductor substrate. A P-well and an N-well inside the semiconductor substrate are formed and isolated by an isolating region. Next, a gate oxide layer and a first polysilicon layer are formed sequentially above the P-well and an N-well. A polysilicon layer doped in-situ with N-type ions. Sequentially, a first oxide layer is deposited and a first photoresist layer is formed on the polysilicon layer above P-well region, wherein etching respective patterns on the first oxide layer and the polysilicon layer. An amorphous silicon layer doped with P-type ions by implanation is formed over the gate oxide layer and the first oxide layer above the semiconductor substrate. After forming a second oxide layer on the amorphous silicon layer. A SOG (spin-on glass) layer is deposited above the substrate, and then the SOG (spin-on glass) layer, major second oxide layer and a portion of amorphous silicon layer are removed until the first oxide layer is exposed by chemical mechanical polishing. Next, first etch bulgy P,-type amorphous silicon layer until the amorphous silicon layer surface is smooth, and then etch back the first dielectric layer and second dielectric layer. Finally, respectively forming a P,-type gate above the N-well and a N,-type gate on the P-well.