Non-volatile semiconductor memory device

Abstract

A semiconductor memory device having nonvolatile memory cells of a single-element type. The nonvolatile memory cells have a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. An impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode.