The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2001
Filed:
Aug. 03, 1999
Chia-Chen Liu, Hsinchu, TW;
Ling-Sung Wang, Hsinchu, TW;
Abstract
The present invention provides a cell structure of an electrically programmable read only memory (EPROM) which includes an EPROM gate structure, a source junction region, a drain junction region, a first dielectric layer, a self-aligned common source line, a self-aligned drain contact, a second dielectric layer, and a conductive line. The EPROM gate structure is on a portion of the substrate. The source junction region is in the substrate located on a first lateral side, namely the left side in the figure, of the EPROM gate structure. The drain junction region is in the substrate located on a second lateral side, namely the right side in the figure, of the EPROM gate structure. The first dielectric layer covers on top and sidewalls of the EPROM gate structure. The self-aligned common source line neighbors the first dielectric layer and is above the substrate on a portion of the source junction region. The self-aligned drain contact neighbors the first dielectric layer, and is above the substrate on a portion of the drain junction region. The second dielectric layer covers the first dielectric layer, the self-aligned common source line, and the self-aligned drain contact. The conductive line is on the second dielectric layer and communicates to the self-aligned drain contact.