The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2001

Filed:

Dec. 31, 1998
Applicant:
Inventors:

Ricardo Ramirez, Cupertino, CA (US);

Mike Morrison, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/500 ; G06F 9/38 ;
U.S. Cl.
CPC ...
G06F 1/500 ; G06F 9/38 ;
Abstract

A microprocessor capable of delaying the deallocation of an arithmetic flags register is described. A system processes instructions of a first instruction set architecture which has an arithmetic flags register. The system also processes instructions of a second instruction set architecture which is not compatible with the first instruction set architecture. In order to process a first instruction of the first instruction set architecture that implicitly updates the arithmetic flags register, the arithmetic flags register shares a physical destination register with a general register containing a result for the first instruction. An instruction that does not update the arithmetic flags but would deallocate the register containing the arithmetic flags triggers the delayed deallocation mechanism of the present invention.


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