Synchronous data sampling circuit

Abstract

A synchronous data sampling circuit and method are provided by which it is possible to sample four data items during one cycle of a clock signal. In the synchronous data sampling circuit a first pulse signal generator receives the clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. A second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal. A first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. A second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to a rising or falling edge of the first pulse signal. A third sampling unit samples third data input through the input port and outputs the sampled third data to the output port in response to the rising edge of the clock signal. A fourth sampling unit samples fourth data input through the input port and outputs the sampled fourth data to the output port in response to the rising or falling edge of the second pulse signal. As a result, four data items are sampled during one cycle of the clock signal, doubling the data sampling efficiency, as compared to the data sampling efficiency of a conventional dual data rate (DDR) method.