The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2001
Filed:
Dec. 10, 1999
James S. Blomgren, Austin, TX (US);
Terence M. Potter, Austin, TX (US);
Stephen C. Horne, Austin, TX (US);
Michael R. Seningen, Austin, TX (US);
Anthony M Petro, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.