The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2001
Filed:
Nov. 22, 1999
Applicant:
Inventors:
Mark S. Rodder, University Park, TX (US);
Sunil V. Hattangady, McKinney, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 2/18238 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 2/18238 ; H01L 2/1336 ;
Abstract
A gate stack (,) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (,) is formed over the silicon substrate (,). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (,) over the high-k dielectric (,). A conductive layer (,) is formed over the nitride layer (,) forming the gate electrode.
Quick Actions:
Rodder, Mark. (2001). Process for polycrystalline silicon gates and high-k dielectric compatibility (U.S. Patent No. 6251761). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6251761
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile