High speed test pattern evaluation apparatus

Abstract

A high speed evaluation apparatus for evaluating a test pattern produced for a semiconductor test system or performing a diagnostic test on a design of the semiconductor device, based on logic simulation data produced in a design stage of the semiconductor device through a CAD (computer aided design) process, without using an actual semiconductor test system or a semiconductor device. The apparatus includes an LSI tester simulator for generating a test pattern for testing a semiconductor device and an expected value pattern for comparing the output of the semiconductor device which is responsive to the test pattern, a cycle-event converter for converting the test pattern from the LSI tester simulator in a cycle base form to a test pattern of an event base form, a first memory for storing the event based test pattern from the cycle-event converter, a second memory for storing a predetermined amount of input/output data of the semiconductor device from a dump file storing data resulted from executing a logic simulation on the semiconductor device in the design stage of the semiconductor device under the CAD process, and a comparator for synchronizing the data stored in the first and second memories by comparing the timing relationship between the two and extracting output data of the device under test from the dump file corresponding to the test pattern from the LSI tester simulator.