The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2001
Filed:
May. 27, 1999
Fumitomo Matsuoka, Kawasaki, JP;
Kunihiro Kasai, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
The present invention is a semiconductor device having an element isolation structure of STI, in which after the formation of the STI trench, a silicon nitride film is left over only on the side wall portion of the trench, to form a side wall. Further, ions are implanted from the bottom surface of the trench on which the side wall is formed, and thus a high-concentration punch-through suppression region having the same conductivity as that of the substrate (or well) and a concentration higher that the impurity concentration of the other section close to the substrate (or well), is formed selectively only in the section of the substrate (or well) which is near the bottom surface of the trench. In this manner, the punch-through suppression region can be formed only in the bottom portion of the STI in a self-alignment manner by the thickness of the side wall. With this structure, even if the STI has a shallow or fine element isolation structures the punch-through between diffusion layers can be suppressed, and the occurrence of a junction leak between the high-concentration diffusion layer region and the well can be prevented. Therefore, a well structure of a low capacitance, which is suitable for a high-speed operation device, can be designed.