The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 19, 2001
Filed:
May. 26, 1998
Applicant:
Inventors:
Evanthia Papadopoulou, Elmsford, NY (US);
Mark Alan Lavin, Katonah, NY (US);
Gustavo Enrique Tellez, Cornwall on Hudson, NY (US);
Archibald John Allen, Shelburne, VT (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
An efficient computer implemented method computes critical area for via blocks in Very Large Scale Integrated (VLSI) circuits. The method is incremental and takes advantage of the hierarchy in the design. In order to increase the efficiency further we use the L,or the L,metric instead of the Euclidean geometry.
Quick Actions:
Papadopoulou, Evanthia. (2001). Incremental method for critical area and critical region computation of via blocks (U.S. Patent No. 6247853). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6247853
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