Method and system for pipe stage gating within an operating pipelined circuit for power savings

Abstract

A method and system for power savings within a pipelined design by performing intelligent stage gating. The present invention recognizes that not every operand applied to the input of a pipeline requires a recomputation in the different pipeline stages. Circuitry is used to generate a signal, C, indicating that this condition holds. C is then used to gate the register bank at the input of the first pipeline stage thereby potentially saving power in the register bank. Moreover, C can also be stored in a register, the output of which: a) gates the register bank of the second stage; and b) connects to another register to store signal C to be used in the third stage. Power savings is provided by not clocking the register circuit of the stage, and in some instances, power is saved within the stage's associated combinational logic. In one embodiment, a register (to store C) is added in each stage of a pipeline to use C as a gating signal in the subsequent stage. This yields a structure in which signal C propagates through the pipeline in synchronization with the clock, successively gating the associated register banks. The value of C is generated whenever the output of the stage is inconsequential. For example, the output can be inconsequential in cases when duplicate operands are received in back-to-back clock cycles. Also, in maximum and minimum cases a operand that is not larger or smaller, respectively, than the largest or smallest previously received operand can yield an inconsequential result.