The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2001

Filed:

Jun. 19, 2000
Applicant:
Inventor:

Tsong-Minn Hsieh, Miao-Li, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18247 ;
U.S. Cl.
CPC ...
H01L 2/18247 ;
Abstract

A method of manufacturing a self-aligned split-gate flash memory cell with high coupling ratio is disclosed. A polysilicon spacer is first formed on each of the inner walls between the two select gates on which a dielectric layer is formed. A drain and a source are next formed adjacent to each of the outer walls of the two select gates and between the two polysilicon spacers, respectively. A silicon oxide layer is deposited. A predetermined thickness of the silicon oxide layer is then removed and the dielectric layer is removed down to a predetermined thickness by using a dry etching process. Finally, a control gate is formed above the polysilicon spacers.


Find Patent Forward Citations

Hsieh, Tsong-Minn. (2001). Method of manufacturing a split-gate flash memory cell with polysilicon spacers (U.S. Patent No. 6245614). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6245614

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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