Buried channel quasi-unipolar transistor

Abstract

A buried channel lateral quasi-unipolar transistor having low flicker or 1/f noise has a bulk region that forms the base of the buried quasi-unipolar transistor. A drain region is implanted into the bulk region to form a drain/collector. A source region is placed at a distance from the drain region and is implanted in the bulk region to form a source/emitter. A channel layer is implanted in the bulk region between the source region and the drain region to provide a low resistivity conduction channel between the drain/collector and the source/emitter. A gate oxide is placed on the surface of the semiconductor substrate immediately above the channel layer. Then a gate electrode of a conductive material such as polycrystalline silicon doped to with a material having a conductivity opposite that of the source/drain deposited on the gate oxide above the channel region. A biasing voltage source connected between the gate electrode and the bulk region to lower a built-in voltage of the quasi-unipolar transistor. The buried channel lateral quasi-unipolar transistor further may have an overlayer implanted between the channel layer and the surface of the semiconductor substrate to form the buried channel layer rather than at the surface of the semiconductor substrate. The buried channel lateral quasi-unipolar transistor may be placed in a diffusion well into which a bulk region is implanted.