Non-volatile memory cell capable of being programmed and erased through substantially separate areas of one of its drain-side and source-side regions

Abstract

In accordance with the present invention, a low VCC operational non-volatile memory cell includes a drain region and a source region separated by a channel region. A tunneling dielectric layer extends over the channel region and a portion of the drain and source regions. A floating gate extends over the tunneling dielectric. An insulating layer extends over the floating gate, and a control gate extends over the insulating layer. The channel region is implanted with a relatively low dosage of channel threshold enhancement impurities or halo impurities to obtain a low initial Vt in the range of, for example, OV to 0.8V. The low initial Vt enables a low program Vt target ,e.g., 4V or less, which in turn enables the use of double-diffused N+, N− drain or source junctions with the N+ region being inside the N− region. The memory cell is programmed through hot electron injection from a channel region near the N− region to the floating gate, and is erased through Fowler-Nordheim tunneling of electrons from the floating gate to an area of the N+ region near the N− region. Thus, the N− region separates the erase area in the N+ region from the program area in the channel region.