The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2001
Filed:
Apr. 13, 1999
Sheng Teng Hsu, Camas, WA (US);
Chien Hsiung Peng, Vancouver, WA (US);
Jong Jan Lee, Camas, WA (US);
Abstract
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb,Ge,O,FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb,Ge,O,FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.