The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2001
Filed:
Oct. 07, 1999
Jyh-Ren Wu, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method for fabricating a borderless via on a semiconductor device is described in which a substrate comprising a dielectric layer is provided. A conductive layer, a barrier layer and a metal layer are sequentially formed on the dielectric layer. A first photoresist pattern is further formed to cover the metal layer. A first etching step is then conducted using the barrier layer as an etching end point and the photoresist pattern as an etching mask. The tungsten metal layer is etched to form a tungsten metal plug in the first etching step. Thereafter, a second photoresist pattern is formed on the barrier layer, partially covering the first photoresist pattern and the barrier layer. A second etching is then conducted on the barrier layer and the metal layer to form a conductive line, using the first photoresist pattern and the second photoresist pattern as etching masks. The first and the second photoresist patterns are then removed. An inner metal dielectric layer is further formed enclosing the tungsten metal plug, the barrier layer and the conductive line. The tungsten metal plug enclosed by the inner metal dielectric layer is a borderless via structure.