The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2001

Filed:

Aug. 02, 1999
Applicant:
Inventors:

Shigetaka Kumashiro, Tokyo, JP;

Kiyoshi Takeuchi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/166 ;
U.S. Cl.
CPC ...
H01L 2/166 ;
Abstract

In a reverse profiling method, first and second processes produce first and second groups of MOSFETs, respectively. In the first process, channel impurities are implanted into a semiconductor substrate after implantation of source/drain impurities and annealing of the semiconductor substrate. Consequently, the annealing modulates channel impurity density distribution. On the other hand, in the second process, source/drain impurities are implanted into a semiconductor substrate after implantation of channel impurities and annealing of the semiconductor substrate. The annealing does not modulate channel impurity density distribution in the second process. First threshold voltage-gate length characteristics of the MOSFETs of the first group are found. Similarly, second threshold voltage-gate length characteristics of the MOSFETs of the first group are found. Finally, modulated impurity density distribution of the MOSFET of the first group is found on the basis of said first threshold voltage-gate length characteristics and said second threshold voltage-gate length characteristics.


Find Patent Forward Citations

Kumashiro, Shigetaka. (2001). Reverse profiling method for profiling modulated impurity density distribution of semiconductor device (U.S. Patent No. 6242272). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6242272

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