The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2001

Filed:

Nov. 29, 1999
Applicant:
Inventors:

Naoaki Aoki, Austin, TX (US);

Sang Hoo Dhong, Austin, TX (US);

Nobuo Kojima, Austin, TX (US);

Joel Abraham Silberman, Somers, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3568 ;
U.S. Cl.
CPC ...
H03K 3/3568 ;
Abstract

A true/complement signal generator for a dynamic logic circuit having a dynamic node is disclosed. The true/complement signal generator for a dynamic logic circuit having a dynamic node includes a cascaded inverter circuit, a first half-latch circuit, and a second half-latch circuit. The cascaded inverter circuit, which is connected to the dynamic node, includes a first inverter connected in series with a second inverter. Connected to an output of the second inverter of the cascaded inverter circuit, the first half-latch circuit generates an output signal. Connected to an output of the first inverter of the cascaded inverter circuit, the second half-latch circuit generates a complement output signal.


Find Patent Forward Citations

Aoki, Naoaki. (2001). Method and apparatus for generating true/complement signals (U.S. Patent No. 6239620). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6239620

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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