Simulation-based method for estimating leakage currents in defect-free integrated circuits

Abstract

A method for operating a data processing system to provide an estimate of the leakage current expected from an integrated circuit having a known test vector applied thereto. The method generates a graph having a first node connected to a terminal maintained at a first power supply potential and a second node connected to a terminal maintained at a second power supply potential, the first and second power supply potentials having a potential difference of V,. Each edge represents a source-drain connected transistor connected between two nodes as a switch having a resistance that depends on whether the transistor is “on” or “off” when the test signals are present. Each node in the graph is assigned a value of 0 or 1, together with the strength of that value. The assignment process also verifies that the circuit is in a valid static state. A leakage current estimate is generated for each path connecting the first and second nodes, and estimates are combined to arrive at the estimate for the integrated circuit. In one embodiment, the leakage current is calculated using an equation having eight components. Four of these represent the leakage current arising from N-type transistors in the circuit and the other four represent the leakage current arising from P-type transistors in the circuit.